The present invention relates to error correcting coding and decoding. More specifically it relates to generating error correcting cyclic codes and error correcting decoding methods.
Error correction of digital codes is widely used in telecommunications and in transfer of information such as reading of data from storage media such as optical disks. Detection of errors can take place by analyzing symbols that were added to the information symbols during coding. The relation between information symbols and the added coding symbols is determined by a rule. If after reception of the symbols such relation between the symbols as provided by the rule no longer holds, it can be determined that some of the symbols are different or in error compared to the original symbols. Such a relationship may be a parity rule or a syndrome relationship. If the errors do not exceed a certain number within a defined number of symbols it is possible to identify and correct these errors. Known methods of creating error correcting codes and correction of errors are provided by BCH codes and the related Reed-Solomon (RS) codes. These codes are known to be cyclic codes. Error-correction in RS-codes usually involves calculations to determine the location and the magnitude of the error. These calculations in RS-codes can be time and/or resource consuming and may add to a coding latency.
Accordingly methods that can generate and decode cyclic error correcting codes in a faster or easier way are required.